Digital System Test And Testable Design: Using ... Apr 2026

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .

Random and deterministic test generation methods, plus sequential circuit test generation. Digital System Test and Testable Design: Using ...

Gate-level faults, fault collapsing, and structural modeling in Verilog. This book is widely used as a primary

Scan architectures, RT-level scan design, and Boundary Scan (JTAG). RT-level scan design

Memory fault models, MBIST (Memory BIST) methods, and functional procedures.

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.